ess technology, inc. sam0387-04 11 01 1 ess technology, inc. ES2841/es2840 pci integrated lan v.90/v.92 modem product brief description the ES2841/es2840, ess technology?s first lan plus host- based tel e drive a modem chip for the pci bus, provides des kt op and notebook computers with greater connectivity to bo th packet networks and telephone networks. the ES2841 / es2840 solution uses a solid-state daa instead of a traditional transformer daa. the chipset consists of the ES2841 la n modem chip and the es2840, its accompanying high- voltage, solid-state daa device. the ES2841 maximizes integration and reduces the external component bom cost to a minimum. the ES2841 device combines into a single-chip a host-based v.90/v.92 modem, modem control buffers, modem codec, and an ieee 802.3-compatible ethernet media access controller (mac) with an analog phoneline interface and a pci bus interface. this advanced high-level device integration allows the ES2841 to be used as a host-based modem and lan solution for desktop and notebook systems requiring either a modem connection or a 10/100 ethernet connection. the ES2841 is also capable of providing a home network connection that complies with the home phoneline networking alliance (homepna) 1-mb/ s (hpna1.0) specification. the ES2841 lan feature supports 100base-tx (100-mb/s mode) and 10base-t (10-mb/s mode) full-duplex operations. the ES2841 includes a media independent interface (mii) and reduced mii (rmii), enabling it to interface with an external phy transceiver used for either a lan or hpna-based chipset. the es284 modem sends and receives data and fax information and supports the telephone answering machine (tam) feature. with its built-in acpi d3 cold wake on-lan and wake on-ring support, the ES2841 is an ideal modem solution for notebooks and battery-operated devices. the ES2841 modem provides the interface and control logic needed to transfer data between its serial i/o terminals and the pci interface. the ES2841 delivers a high modem connectivity rate and high throughput without the need of a dedicated dsp. it also integrates a low-voltage, solid-state daa that supports both worldwide homologation and data/fax/voice call discrimination. with the addition of an external high-voltage, solid-state daa, the ES2841 provides a very cost-effective modem/lan solution for add-on card, motherboard, and mini-pci card implementations. the es2840 high-voltage daa device handles the line monitoring and filtering functions, while also protecting the signaling characteristics, performing all of the ac and dc functions and interfacing with the line side of tip and ring operations. the ES2841 is available in a 128-pin low-profile quad flat pack (lqfp) package. the es2840 is available in an industry standard 20-pin super small outline pack (ssop) package. features ? v.90/v.92 analog data/fax/tam modem ? data mode capabilities: ?? v.90/v.92: 56 kbps ?? itu-t v.34: 33.6 kbps and fallbacks ? fax mode capabilities: ?? itu-t v.17, v.29, v.27ter, and v.21ch2 ?? group 3 (tia/eia-578 class 1 and class 2) ? requires minimum 166-mhz pentium with mmx technology ? integrated modem codec and analog front end ? 16-bit adc and dac with built-in anti-aliasing and reconstruction filters ? integrated low-voltage daa circuit ? interface to the es2840 high-voltage daa ? 10/100-mb/s lan or 1-mb/s hpna networking capability ? integrated on-chip 1/10/100-mbps mac controller capable of interfacing with 10base-t phy transceiver and with 100base- tx phy transceiver ? mii for connecting to external 10/100-mbps phy transceiver ? rmii for connecting to external 10/100-mbps phy transceiver ? full-duplex operation supported in mii and rmii ports with independent transmit (tx) and receive (rx) channels ? support for ieee 802.3x flow control and ieee 802.3u autonegotiation for 10base-t and 100base-tx ? eeprom interface for subsystem id and subsystem vendor id ? acpi and pci power management standard-compliant ? wake-on-ring and wake-on-lan capability ? on-chip fifos for pci bus and both rx and tx state machines ? supports both rj-11 tip and ring connection and rj-45 lan/ ethernet connection ? pc99/pc2001-compliant with support for v.250, v.251, and v.253 commands ? worldwide homologation modem driver support ? microsoft windows ? 98/se/me/2000 ? microsoft windows nt 4.0 lan driver support ? nic drivers for netware 3.x and 4.x networks (16-bit and 32-bit odi) ? microsoft windows networks (ndis 2.0, 4.0, and 5.0) ? packet driver ? linux
2 sam0387-04 11 01 ess technology, inc. ES2841/es2840 product brief pinout pinout figure 1 shows the ES2841 and 2840 pinout diagrams. figure 1 ES2841 and es2840 pinout diagrams 1 dspk p f 10 p f 9 p f 8 k t xp o s c o vcm vref rxn krxn krxp d3 d4 t x c l k / r e f c l k r x d 1 r x d 2 va u x r x d 0 r xe r / r x _ e r r x d v / cr s _ d v c o l / spee d 10 gnd m d i o / se c l k m dc / r m ii _ m o d e r x d 3 k_en/secs pf0 t x n t xp a g nd av dd pf2 pf3 pf4 pf5 t r i dr v g nd o s c i link_st2 p w r _ r s t b r s t _ p h yb k t x n d2 ES2841s a d 16 a d 17 a d 18 a d 19 a d 21 a d 22 a d 23 g nd i d se l cbe3# v dd ad24 ad25 ad28 ad26 ad27 ad29 ad30 ad31 ad3 cbe0# ad4 i rd y # g nd f r a m e # c be 2# vdd 96 97 64 128-pin lqfp ad6 ad7 vdd ad8 ad9 ad10 a d 11 a d 12 a d 13 a d 14 a d 15 33 32 g nd c be 1# pa r s t o p # d evse l# t rd y # pme# vauxp/wol pciclk clkrun# pcignt# pcireq# rst# inta# 128 vaux g nd d 1 txen txd2 65 a d 20 ad5 rxp d5 d6 ad0 ad1 ad2 gnd va u x g nd r x c l k i r q # cr s l i n k _ s t 1 va u x pf7 vdd gnd se rr # g nd v dd vdd gnd sedo/txd0 sedi/txd1 txd3 vaux es2840j 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 clim d1 d2 vdd d3 d4 lcom d5 d6 cpx tout gain line linei ina inb ter1 ter2 set cpx\ 20-pin ssop
ess technology, inc. sam0387-04 11 01 3 ES2841/es2840 product brief pin descriptions pin descriptions table 1 lists the ES2841 pin descriptions, and table 2 lists the es2840 pin descriptions. table 1 ES2841 pin descriptions names pin numbers i/o definitions idsel 1 i id select. gnd 2, 3, 22, 23, 52, 53, 72, 85, 86, 116, 117 g digital ground. vdd 12, 13, 37, 38, 126, 127 p 3.3v digital power supply. ad[31:0] 4:11, 24:28, 33:35, 39:46, 118:125 i/o address and data lines from the pci bus. c/be[3:0]# 14, 21, 36, 128 i/o pci command/byte enable. during address phase of a transaction, these pins define the bus command. during data phase, these pins define the bus enable. frame# 15 i/o cycle frame. irdy# 16 i/o initiator ready. trdy# 17 i/o target ready. devsel# 18 i/o device select. stop# 19 i/o stop transaction. par 20 i/o parity. serr# 29 od system bus error. pf[10:7] and pf[5:2] 30:32, 47:51 i/o general-purpose programmable bidirectional flag. these pins can be used for interfacing with a telephone or other device, performing such functions as caller id, etc. refer to pin descriptions for pins 54, 108, and 109 for preprogrammed telephone interface pins. d5 and d6 54, 55 o d6 isolation signal output. d[4:3] 56, 57 i receive data signal inputs from external hybrid interface. krxp 58 o daa analog differential receive positive output. krxn 59 o daa analog differential receive negative output. rxn 60 i codec analog differential receive negative input. the dc level is vcm, and the full- scale input is either 2.2vp-p5% or 1.1vp-p5%, depending on the gain setting. rxp 61 i codec analog differential receive positive input. the dc level is vcm, and the full- scale input is either 2.2vp-p5% or 1.1vp-p5%, depending on the gain setting. vref 62 o voltage reference bypass. has a range of 1.235v5%. bypass to agnd with 0.1-mf ceramic chip capacitor parallel with 10-mf tantalum capacitor. vcm 63 o common mode voltage bypass. has a range of 2.16v5%. bypass to agnd with 0.1-mf ceramic chip capacitor parallel with 10-mf tantalum capacitor. d[2:1] 64, 65 o transmit signal outputs to external hybrid interface. ktxp 66 i daa analog differential transmit positive input. ktxn 67 i daa analog differential transmit negative input.
4 sam0387-04 11 01 ess technology, inc. ES2841/es2840 product brief pin descriptions txn 68 o codec analog differential transmit negative output. the dc level is vcm, and the full-scale input is either 2.8vp-p5% or 1.4vp-p5%, depending on the gain setting.the maximum loading is 1.2k w, in parallel with 20 pf for modem applications. txp 69 o codec analog differential transmit positive output. the dc level is vcm, and the full-scale input is either 2.8vp-p5% or 1.4vp-p5%, depending on the gain setting.the maximum loading is 1.2k w, in parallel with 20 pf for modem applications. agnd 70 g analog ground. avdd 71 p 5v analog power supply. osci 73 i crystal clock input. osco 74 o crystal clock output. vaux 75, 88, 89, 104, 105 p 3.3v vaux power supply for wake-on-ring and wake-on-lan. link_st1 76 i link status interface input from phy. phy_rstb 77 o reset output to phy; will follow pwr_rstb and remain active for 1.3 msec after pwr_rstb. can be toggled by bit 7 of lan_io register [4ah]. pwr_rstb 78 i power-on reset. this is an active-low input signal when a power-on reset event occurs. rxer 79 i receive error input for mii mode. indicates that external phy transceiver has detected coding errors in receive data frame currently being transmitted to rxd[3:0]. rxer is ignored while rx_dv is deasserted. rx_er i receive error input for rmii mode. indicates that external phy transceiver has detected coding errors in receive data frame currently being transmitted to rxd[1:0]. rx_er is ignored while rx_dv is deasserted. rxdv 80 i receive data valid. crs_dv i carrier sense/receive data valid. asserted asynchronously by the phy when the receive medium is nonidle. in 10base-t mode, carrier is detected when squelch is passed in rmii mode. col 81 i collision. when selected as col, asserted output whenever a collision is detected. speed10 i speed select pin. acts as toggle for 10-mb/s and 100-mb/s operation for external phy transceiver in rmii mode. crs 82 i carrier sense input. rxclk 83 i receive clock input. provides the nibble rate clock timing reference for the output transfer of rxdv, rxd[3:0] and rxer/rx_er signals and operates at 25/2.5 mhz. irq# 84 i interrupt request. txclk 87 i transmit clock input. when selected as txclk, provides timing reference for transfer of the transmitted data and operates at 25/2.5 mhz. refclk i reference clock input. when selected as refclk, provides continuous clock timing reference for crs_dv, rxd[1:0], txen, txd[1:0], and rx_er. operates at 50 mhz 50 ppm, with a duty cycle between 35% and 65% in rmii mode. rxd[3:0] 90:93 i receive data pins [3:0]. when in rmii mode, only rxd[1:0] are defined. table 1 ES2841 pin descriptions (continued) names pin numbers i/o definitions
ess technology, inc. sam0387-04 11 01 5 ES2841/es2840 product brief pin descriptions mdio 94 i/o when the mdio function is selected, this pin functions as the mii management data i/o pin. it acts as an output during the header portion of management frame transfers and during the data portion of write operations. it also acts as an input dur- ing the data portion of read operations. seclk o serial eeprom data clock input. mdc 95 o when the mdc function is selected, this pin functions as the mii management data clock pin. it runs up to 2.5 mhz. rmii_mode i rmii_mode enable. the ES2841 supports both mii and rmii modes. when the rmii_mode signal is high, rmii mode is supported. tridrv 96 o tri-state output pin connected to the input pin of hpna phy to tri-state output of hpna phy. when asserted high, this pin tri-states all outputs except open-drain outputs. link_st2 97 i link status interface input from (second) hpna phy. txen 98 o transmit enable. indicates that the mac is presenting valid data on txd[3:0]. txen transitions are latched on the falling edge of refclk. sedo 99 o serial eeprom data input. txd[0] o transmit data output pin 0. sedi 100 i serial eeprom data output pin with an internal pullup. txd[1] o transmit data output pin 1. txd[3:2] 101, 102 o transmit data pins 2 and 3 in mii mode. not defined in rmii mode. k_en 103 i on-chip low-voltage daa enable input. pullup to v aux to enable the on-chip low- voltage daa module. strap option pin latched at power-on reset. secs o serial eeprom port chip select output. pme# 106 od power management enable interrupt output to wake up the system. vauxp 107 i v aux support detection pin. v auxp is driven high at reset to indicate that acpi is supported with d3 cold state. no support when driven low. strap option pin latched at power-on reset. wol o wake-on-lan signal output. the ES2841 asserts this signal if a change is detected in link status, magic packet ? , or sample frame events. pf0 108 i general-purpose programmable input pin 0. dspk 109 o modem speaker digital output when selected. clkrun# 110 i/o clkrun# is an i/o pin for pci clock status and an output to start or accelerate clock function. pcignt# 111 i pci grant input. pcireq# 112 o pci request output. rst# 113 i pci bus reset. inta# 114 od interrupt a request output, active-low. inta# is the level triggered interrupt pin ded- icated to servicing internal device interrupt requests. pciclk 115 i pci bus clock input. table 1 ES2841 pin descriptions (continued) names pin numbers i/o definitions
6 ? 2001 ess technology, inc. sam0387-04 11 01 ES2841/es2840 product brief ordering information no part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ess technology, inc. ess technology, inc. makes no representations or warranties regarding the content of this document. all specifications are subject to change without prior notice. ess technology, inc. assumes no responsibility for any errors contained herein. (p) u.s. patents pending. tele drive is a registered trademark of ess technology, inc. all other trademarks are owned by their respective holders and are used for identification purposes only. ess technology, inc. 48401 fremont blvd. fremont, ca 94538 tel: (510) 492-1088 fax: (510) 492-1898 ordering information table 2 es2840 pin description name pin numbers i/o definitions clim 1 i/o complex impedance termination pulldown. d[1:2], d[5:6] 2:3, 8:9 i isolation signal inputs. vdr 4 p dc supply input. d[3:4] 5, 6 o isolation signal outputs. lcom 7 o line side common ground reference. cpx, cpx\ 10, 11 i/o dc current limit mode pulldown (pin 10) and 600 w impedance termination pull- down (pin 11) set 12 o dc reference filter. ter[2:1] 13, 14 i/o voltage termination controls. in{a:b] 15, 16 i ring and caller id signal inputs. linei, line 17, 18 i line ac signal input (pin 17) and line dc signal input (pin 18). gain 19 o transmit gain control. tout 20 o transmit gain output. part numbers descriptions packages ES2841s pci v.90/v.92 hsp modem lan 128-pin lqfp es2840j modem high-voltage daa 20-pin ssop
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